The Instruction set architechture (ISA) is plays an important role
in the microprocessors. There are different instruction set architechture
microprocessors available in them market, they are:
1. Complex Programming Instruction Set Computer (CISC)
This was first ISA. In the complex instruction set computer (CISC)
instruction set is complex instruction which will take long time to execute.
Complex instruction may consist of opcode addressing mode operand etc. The
execution speed will be slow. X86 architechture is the example.
2. Reduced Instruction Set Computer (RISC)
In the reduced instruction set computer (RISC), the instruction set
will be small and execution speed will be fast. The implementation is simple
and does not require complex architechture. RISC is widely used in embedded
applications. SHARC and POWERPC use RISC.
There are some differences between CISC and RISC:
CISC
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RISC
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Very large instruction sets reaching up to and above three hundred
separate instruction.
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Small set of instruction.
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Performance was improved by allowing the simplification of program compilers,
as the range of more advanced instructions available led to less refinements
having to be made at the compilation process. However, the complexity of the
processor hardware and architecture that resulted can cause such chips to be
difficult to understand and program for, and also means they can be expensive
to produce.
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Simplified and reduced instruction set, numbering one hundred instruction
or less. Because of simple instructions, RISC chips requires fewer
transistors to produce processors. Also the reduced instruction set means
that the processor can execute the instructions more quickly, potentially
allowing forgreater speeds. However, only allowing such simple instructions
means a greater burden is placed upon the software itself. Less instruction in
the instruction set means a greater emphasis on the efficient writing of
software with the instructions that are
available.
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More specialized addressing
modes and registers also being implemented, with variable length instruction
codes.
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Addressing modes are simplified
back to four or less, and the length of the codes is fixed in order to allow
standardization across the instruction set.
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Instruction pipelining can not
be implemented easily.
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Instruction pipelining can be
implemented easily.
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Many complex instructions can
access memory, such as direct addition between data in two memory locations.
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Only LOAD/STORE instructions
can access memory.
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Mainly used in normal PC’s,
workstations and servers.
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Mainly used for real time
applications.
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CISC systems shorten time by
reducing the number of instruction per program.
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RISC systems shorten execution
time by reducing the clock cycles per instruction (i.e. simple instructions
take less time to interpret.
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Examples of CISC Processors:
Intel x86.
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Examples of RISC Processors:
Atmel AVR, PIC, ARM.
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Some differencess
between Von-Neumann and Harvard:
VON
-NEUMANN
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HARVARD
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It is named by early computer
scientist John Von Neumann.
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This name is oridinated by
“Harvard Mark I” a relay based old computer.
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The computer has single storage
system for storing data as well as program to be executed.
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The omputer has two separate
memories for storing data and program.
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Processor needs two clock
cycles to complete an instructions is not possible with this architecture.
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Procesor can complete an
instruction in one cycle if appropriate-pipelining strategies are
implemented.
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In the first clock cycle the
processor gets the instruction from memory and decodes it. In the next clock
cycle the required data is taken from memory. For each instruction this cycle
repeats and hence needs two cycles to complete an instruction.
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In the first stage of pipeline
the instruction to be executed can be taken from program memory. In the
second stage of pipeline data is taken from the data memory using the decoded
instruction or address.
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This is a relatively older
architecture and was replaced by Harvard architecture.
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Most of the modern computing
architectures are based on Harvard architecture. But the number of stages in
the pipeline varies from system to system.
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There are other architecture like
Very Long Instruction word (VLIW) and FUSION of RISC and CISC architecture etc.
Microprocessor should be choosen
according to the application for small application you don’t need CISC. You
cannot use RISC for large application. According to the application and
peripherals you are using micro processor should be taken.
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